Wafer Level Chip Scale Packaging (WLCSP) is becoming more prevalent as industry demands smaller and thinner microelectronic packages. WLCSP allows smaller form factors, improved electrical performance and a relatively simpler structure over conventional wire bond or interposer packaging technologies. PacTech offers state-of-the-art wafer bumping and WLCSP solutions such as RDL and copper pillar plating:
Cu pillar bumping with bump diameters as small as 25 microns
Possible metal stacks for pillar Cu, Cu/SnAg, Cu/Ni/SnAg
Bump-on-pad and bump-on-polymer processes
Single and multiple layer Cu redistribution with several polymer repassivation material choices
Applicable on Silicon, Glass and GaN substrates, 100mm to 200mm wafer
Electroplating Example (scroll down)
The goal is to redistribute the connections placed on an insulation layer. The process starts with a passivation layer on top of the insulation layer.
2. Seed Layer
A seed layer, usualy made of sputtered or evaporated metal, is placed on top of the object to create new connection possibilites.
A light-sensitive organic material, the photoresist, is placed on the seed layer. It enables the masking in the next process of photolithography.
Light is used to mask the photoresist and to generate new patterns for connections. Depending on the polarity of the light, materials with be affected differently regarding weakening and toughening.
Into the now masked regions, a thin layer, for example copper or other conductors, is deposited on the seed layer through the electroplating process.
6. Resist Stripping
The mask created through the photolithography is getting stripped from the object so the seed layer can be reworked in the next process.
Undesirable materials, in this case the seed layer, are getting removed from the object, so the seed and copper layer result in the exact same size.
Deposition of the passivation layer. This separates the new positioned electronical connections after masking in the next process of photolithography.
The second masking of this process example. On specific positions, the passivation layer gets removed to create new spaces for the under-bump metallization.
10. Electroless UBM
Stacks of metal layers are placed in the masked spaces between the passivated layer to complete the integrated circuit for different applications.
11. Solder Ball
Solder bumps or copper pillars can be now placed onto the UBM layer for subsequent applications like flip chip.