Laser Assisted Bonding (LAB) and De-bonding (LAdB) as an Advanced Process Solution for Selective Repair of 3D and Multi-die Chip Packages<\/h1><\/div> <\/p>\n<\/div><\/div><\/div><\/div><\/div>
Abstract:<\/strong><\/span><\/h2>\nThis paper describes an advanced method for repairing assembled 3D and multi-die chip packages using a unique process involving laser assisted bonding
\n(LAB) and laser assisted de-bonding (LAdB); i.e. \u201cLAPLACE\u00a0\u00ae\u201d. Using a laser the as medium for inducing the thermal load into a soldered interface of a chipassembly generates many technical advancements with reference to processing, thermal and mechanical stresses and life-time. This paper reveals the basic mechanism and process flow of LAdB involving the characterization of different phases during de-bonding, along with the results of a feasibility study. For the feasibility study, 4 different test substrates were used, a 3D chip-on-chip package, a chip-on-wafer, and 2 different chip-on-board configurations. The impact of sequential single die removal using LAdB, and accompanying chip replacement using LAB were analyzed. The underlying test materials used were Si-chips, with 40 \u03bcm Sn-plated Cu-pillars, and Si-chips placed with 200 \u03bcm SAC305 (Sn 96.5%, Au 3.0%, Cu 0.5%) solder bumps over 5 \u03bcm pads subjected to 5 \u03bcm electroless nickel immersion gold (ENIG). The chips were stacked resulting in up to 6 layers.<\/p>\n
The main question, whether the use of a given number of laser-assisted repair cycles before a solder bond interface would weaken is explored in the current work using a 130 \u03bcm SAC305 solder bump interface. The interface was formed between the plated pads of Si-chip and a printed circuit board (PCB) board with CuNiAu finish.<\/p>\n
Analysis of thermal load\/thermal distribution in the package during the removal and placement sequence were measured using a contactless\/non-invasive thermooptical sensor element. The ensuing impact on the metallurgical properties and acicular intermetallic compound (IMC) layers corresponding to adjacent interfaces after multiple de-bonding and re-bonding steps were analyzed by cross-sectional analysis, scanning electron microsope (SEM), energy-dispersive x-ray spectroscopy (EDX) and optical microscopy. The mechanical stress was identified by an optical surface flatness measurement tool before and after the chip re-placement steps.<\/p>\n
Tests related to thermal cycling, metallurgical analysis and mechanical shear were conducted to finally generate the number of possible chip replacements using LAB and LAdB processes before the soldered interfaces reached a critical limit of stability and reliability. In conclusion potential applications and future prospects of intended reliability and stability are outlined.<\/p>\n
Keywords – laser bonding, de-bonding, chip repair, 2D\/2.5D\/3D package, SCSP, SIP, POP, multi-die, die removal, low-stress<\/em><\/p>\n<\/div><\/div><\/div>
<\/p>\n<\/div><\/div><\/div><\/div><\/div>
Abstract:<\/strong><\/span><\/h2>\nThis paper describes an advanced method for repairing assembled 3D and multi-die chip packages using a unique process involving laser assisted bonding
\n(LAB) and laser assisted de-bonding (LAdB); i.e. \u201cLAPLACE\u00a0\u00ae\u201d. Using a laser the as medium for inducing the thermal load into a soldered interface of a chipassembly generates many technical advancements with reference to processing, thermal and mechanical stresses and life-time. This paper reveals the basic mechanism and process flow of LAdB involving the characterization of different phases during de-bonding, along with the results of a feasibility study. For the feasibility study, 4 different test substrates were used, a 3D chip-on-chip package, a chip-on-wafer, and 2 different chip-on-board configurations. The impact of sequential single die removal using LAdB, and accompanying chip replacement using LAB were analyzed. The underlying test materials used were Si-chips, with 40 \u03bcm Sn-plated Cu-pillars, and Si-chips placed with 200 \u03bcm SAC305 (Sn 96.5%, Au 3.0%, Cu 0.5%) solder bumps over 5 \u03bcm pads subjected to 5 \u03bcm electroless nickel immersion gold (ENIG). The chips were stacked resulting in up to 6 layers.<\/p>\n
The main question, whether the use of a given number of laser-assisted repair cycles before a solder bond interface would weaken is explored in the current work using a 130 \u03bcm SAC305 solder bump interface. The interface was formed between the plated pads of Si-chip and a printed circuit board (PCB) board with CuNiAu finish.<\/p>\n
Analysis of thermal load\/thermal distribution in the package during the removal and placement sequence were measured using a contactless\/non-invasive thermooptical sensor element. The ensuing impact on the metallurgical properties and acicular intermetallic compound (IMC) layers corresponding to adjacent interfaces after multiple de-bonding and re-bonding steps were analyzed by cross-sectional analysis, scanning electron microsope (SEM), energy-dispersive x-ray spectroscopy (EDX) and optical microscopy. The mechanical stress was identified by an optical surface flatness measurement tool before and after the chip re-placement steps.<\/p>\n
Tests related to thermal cycling, metallurgical analysis and mechanical shear were conducted to finally generate the number of possible chip replacements using LAB and LAdB processes before the soldered interfaces reached a critical limit of stability and reliability. In conclusion potential applications and future prospects of intended reliability and stability are outlined.<\/p>\n
Keywords – laser bonding, de-bonding, chip repair, 2D\/2.5D\/3D package, SCSP, SIP, POP, multi-die, die removal, low-stress<\/em><\/p>\n<\/div><\/div><\/div>
\n(LAB) and laser assisted de-bonding (LAdB); i.e. \u201cLAPLACE\u00a0\u00ae\u201d. Using a laser the as medium for inducing the thermal load into a soldered interface of a chipassembly generates many technical advancements with reference to processing, thermal and mechanical stresses and life-time. This paper reveals the basic mechanism and process flow of LAdB involving the characterization of different phases during de-bonding, along with the results of a feasibility study. For the feasibility study, 4 different test substrates were used, a 3D chip-on-chip package, a chip-on-wafer, and 2 different chip-on-board configurations. The impact of sequential single die removal using LAdB, and accompanying chip replacement using LAB were analyzed. The underlying test materials used were Si-chips, with 40 \u03bcm Sn-plated Cu-pillars, and Si-chips placed with 200 \u03bcm SAC305 (Sn 96.5%, Au 3.0%, Cu 0.5%) solder bumps over 5 \u03bcm pads subjected to 5 \u03bcm electroless nickel immersion gold (ENIG). The chips were stacked resulting in up to 6 layers.<\/p>\n
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