Rerouting of pads on a die with metal and dielectric layers to other locations to fulfil the subsequent packaging rules.
Galvanized Cu post with optional Ni diffusion barrier and SnAg cap for low cost, small pitch flip chip connections.
Low-cost mask-less chemical deposition of various metal stacks on wafer surface to serve as intermetallic connection or to enhance product reliability and performance.
Various solder deposition technologies to form solder bump for WLCSP and flip chip interconnects.
Wafer level assembly by attaching of dies or various passive components on wafer surface.
Removal of wafer backside materials for thinner die in final packaging.
Application of various metal stacks via evaporation or sputtering technologies on wafer backside for better die performance.
High precision and accurate singulation of dies on a wafer.
Pac Tech – Packaging Technologies GmbH Am Schlangenhorst 7-9 14641 Nauen Deutschland
PACTECH ASIA SDN. BHD. Plot 14, Medan Bayan Lepas Technoplex Phase 4 Bayan Lepas Industrial Zone 11900 Bayan Lepas, Penang Malaysia
PacTech USA Inc. 328 Martin Ave Santa Clara CA 95050 USA
